1. Field of the Invention
The embodiments of the invention generally relate to microelectronic logic devices and methods of fabrication and more particularly to the design and manufacturing of integrated circuit devices having improved device performance characteristics and improved manufacturing methods.
2. Description of the Related Art
As integrated circuits (ICs) continue to develop and enhance, the number and density of the devices being formed on IC substrates has increased tremendously with the fabrication of ICs having hundreds of millions and approaching billions of devices on a chip being standard in the industry. In conjunction with this increase in the number of devices formed on an IC substrate and the concurrent increase in density of the devices, the dimensions of the devices have dropped significantly. For example, the dimensions of gate thicknesses and channel separation of source and drain elements continues to be minimized such that today, micrometer and nanometer separations of the source, drain, and gate are required. While devices have been steadily reducing in size, the performance of the devices must also be continually maintained or improved. Furthermore, the ease and cost effectiveness with which these ICs are manufactured should also improve.
The integration of planar IC devices with fin field effect transistors silicon-on-insulator complementary metal oxide semiconductor (FinFET SOI CMOS) devices have some advantages for electrostatic discharge (ESD) and analog applications and for the use of existing designs. Conventional techniques of performing this integration include placing the FET gate on top of SOI islands. However, this generally tends to result in large height differences between the FinFET gates and the gates over the planar logic (i.e., the FET gates). As such, this step height difference is a significant problem for lithography and etching and requires several additional manufacturing steps to ameliorate the problem, which tends to increase the overall manufacturing cost. Therefore, there remains a need for a novel method and structure, which provides superior IC device performance while simultaneously achieving ease of fabrication and reduction in manufacturing cost.